A characteristic of high frequency bipolar transconductance-C filters is that the transconductance varies with temperature, and therefore the cutoff frequency varies with temperature. Accordingly, such a filter is typically supplied with an adjusting signal that adjusts the characteristics of the filter so as to compensate for operational variations which would otherwise occur as a result of temperature changes, thereby keeping the transconductance and cutoff frequency from changing due to temperature variations.
Such a filter will typically have one or more capacitors. When the filter is implemented in an integrated circuit, each capacitor of such a filter will have a capacitance that may vary from an intended value, due to the manufacturing process, and notwithstanding tight quality control procedures. Due to the fact that the capacitors on a given chip are all exposed to the same manufacturing process, the capacitance of each will tend to vary from an intended value by substantially the same percentage. Thus, the adjusting signal is usually trimmed in a manner which compensates for any deviation in capacitance. A further consideration is that, in certain applications, there is a need to intentionally and dynamically adjust the cutoff frequency of the filter, and this is typically implemented by intentionally modifying the adjusting signal so as to change the transconductance.
One application which involves all of these considerations is a hard disk drive system in which a read/write head is supported for approximately radial movement across the magnetic surface of a rotating disk, and in which a plurality of concentric tracks on the disk have different data densities. An output signal from the read/write head is coupled through a preamplifier to an integrated circuit, where it is supplied to a read channel circuit that includes a bipolar transconductance-C filter containing at least one capacitor. A known approach for generating an adjusting signal for such a filter is to take a temperature compensating voltage, which is varied with temperature to compensate for transconductance changes due to temperature changes, and to apply the temperature compensating voltage to a voltage-to-current converter circuit, which in turn applies the voltage across a resistor in order to generate a first current.
The first current is supplied to a PMOS programming circuit, which also receives a digital compensation input that represents the adjustment needed in the cutoff frequency of the filter in order to conform the filter to frequencies defined by the data density of the track with which the read/write head is currently aligned. The programming circuit generates a second current having a magnitude which is the magnitude of the first current scaled by a gain, the gain being defined by the digital compensation input. The second current is supplied to an NMOS trimming circuit, which also receives a digital trim input defining the adjustment needed in the filter as a result of any deviation of the capacitance of each filter capacitor from an intended capacitance. The trimming circuit generates a third current having a magnitude which is the magnitude of the second current scaled by a gain, the gain being defined by the digital trim input.
The third current needs to be converted to a voltage, but has a polarity opposite to the polarity needed by the input of a current-to-voltage converter circuit. The third current is therefore supplied to a PMOS mirror circuit, which generates a fourth current that is a mirror image of the third current. The fourth current is supplied to the current-to-voltage conversion circuit, the output of which is a voltage that serves as the adjusting signal to the filter. Although known arrangements of this type have been generally adequate for their intended purposes, they have not been satisfactory in all respects.
More specifically, the need to provide a PMOS current mirror circuit involves extra area and extra power consumption in the integrated circuit. Further, it is difficult to keep such a current mirror circuit operating where it has good noise rejection, and thus the current mirror circuit degrades the power supply rejection ratio (PSRR). Where the process is a 5-volt BiCMOS process that has only 3-volt CMOS, the use of an NMOS trimming circuit makes it necessary to provide logic level translators and to route the digital trim input signals through the translators before they are applied to inputs of the trimming circuit. The translators ensure that the digital inputs to the trimming circuit do not receive a voltage drop from a 5-volt supply which is greater than 3 volts and may damage the trimming circuit.
A further consideration is that the typical programming circuit implements a gain for the second current which is a factor of five or six times the first current, and the range of variation of the second current is further increased by changes in the temperature compensating voltage as a result of temperature variations. Thus, in this known arrangement, the trimming circuit and the current mirror circuit must both be designed to have the capability to handle a wide range of variation in the magnitude of the currents they handle, which increases the complexity, area and power consumption involved in implementing them in an integrated circuit. A further consideration is that the gain adjustment implemented by the NMOS trimming circuit is linear, whereas the capacitance variation for which it compensates is nonlinear.